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A. Dangol

Katholieke Universiteit Leuven

15

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285

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Reliability of a DME Ru Semidamascene scheme with 16 nm wide Airgaps

2021 IRPS | International Reliability Physics Symposium
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12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

2019 VLSIT | Symposium on VLSI Technology
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Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

2018 IEDM | International Electron Devices Meeting
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Ultralow resistive wrap around contact to scaled FinFET devices by using ALD-Ti contact metal

2017 IITC | International Interconnect Technology Conference
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Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

2016 VLSIT | Symposium on VLSI Technology
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二重仕事関数金属ゲートを持つ垂直積層ゲートオールアラウンドSiナノワイヤCMOSトランジスタ【Powered by NICT】

2016
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Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

2014 Japanese Journal of Applied Physics
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Thermal and SF6-plasma treatments for improved (sub-)1nm EOT planar and FinFET-based RMG high-k last devices and enabling a simplified scalable CMOS integration scheme

2013
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