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Hiroaki Arimura

Katholieke Universiteit Leuven

88

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485

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Low Temperature Atomic Hydrogen Treatment for Superior NBTI Reliability—Demonstration and Modeling across SiO 2 IL Thicknesses from 1.8 to 0.6 nm for I/O and Core Logic

2021 VLSIT | Symposium on VLSI Technology
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Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

2021 VLSIT | Symposium on VLSI Technology
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Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-DIT Si-cap-free Gate Stack and Optimizing the Channel Strain

2020 VLSIT | Symposium on VLSI Technology
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(Invited) Stress Simulations of Fins, Wires, and Nanosheets

2020
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Toward high-performance and reliable Ge channel devices for 2 nm node and beyond

2020 IEDM | International Electron Devices Meeting
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(Invited) Si-Cap-Free Low-DIT SiGe Gate Stack for High-Performance pFETs

2020
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Impact of Dummy Gate Removal and a Silicon Cap on the Low-Frequency Noise Performance of Germanium nFinFETs

2020 IEEE Transactions on Electron Devices
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Low-Frequency Noise Assessment of Work Function Engineering Cap Layers in High-k Gate Stacks

2019 ECS Journal of Solid State Science and Technology
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Gate Metal and Cap Layer Effects on Ge nMOSFETs Low-Frequency Noise Behavior

2019 IEEE Transactions on Electron Devices
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Device-Based Threading Dislocation Assessment in Germanium Hetero-Epitaxy

2019 SBMicro | Symposium on Microelectronics Technology and Devices
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