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Bertrand Borot

STMicroelectronics

27

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298

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Variance Analysis in 3-D Integration: A Statistically Unified Model With Distance Correlations

2019 IEEE Transactions on Electron Devices
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Back-end limitations in advanced nodes and alternatives

2017 SISPAD | International Conference on Simulation of Semiconductor Processes and Devices
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Delay partitioning helps reducing variability in 3DVLSI

2016 ESSDERC | European Solid-State Device Research Conference
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Guidelines on 3DVLSI design regarding the intermediate BEOL process influence

2015 S3S | IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
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Test structures for interdie variations monitoring in presence of statistical random variability

2012 ICMTS | International Conference on Microelectronic Test Structures
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Improved CD control for 45-40 nm CMOS logic patterning: anticipation for 32-28 nm

2010 Proceedings of SPIE
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Comparison of Physical Gate-CD with In-Die At-Speed Non-Contact Measurements for Bin-Yield and Process Optimization

2009 Proceedings of SPIE
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Mixed test structure for soft and hard defect detection

2008 ICMTS | International Conference on Microelectronic Test Structures
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Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework

2008 ISQED | International Symposium on Quality Electronic Design
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Using Model for Assessment of Complementary Metal Oxide Semiconductor Technology and Roadmaps as a Pre-Simulation Program with Integrated Circuit Emphasis Model Generator for Early Technology and Circuit Simulation

2008 Japanese Journal of Applied Physics
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