Test structures for interdie variations monitoring in presence of statistical random variability

We study the limitations of single transistor test structures for Process Variations monitoring in presence of statistical random variability, and compare them with transistor array structures in 45 CMOS technology. By optimizing transistor array design considering statistical variability, layout effects, and interconnect parasitics, we first estimate and then verify on silicon that x5 reduction of statistical variability and excellent correlation with ring oscillator frequency that can be reached for array structure. Transistor arrays are demonstrated to be well suited for monitoring impact of process variations, whether it is die-to-die, or wafer-to-wafer.