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A. Ayres
A. Ayres
STMicroelectronics
Electronic engineering
Spice
Monte Carlo method
Scaling
Electronic circuit
6
Papers
7
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Variance Analysis in 3-D Integration: A Statistically Unified Model With Distance Correlations
2019
IEEE Transactions on Electron Devices
A. Ayres
Olivier Rozeau
Bertrand Borot
Laurent Fesquet
Perrine Batude
Laurent Brunet
Maud Vinet
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Citations (2)
Dense N over CMOS 6T SRAM cells using 3D Sequential Integration
2017
VLSIT | Symposium on VLSI Technology
C-M. V.
C. Fenouillet-Beranger
Melanie Brocard
Olivier Billoint
G. Cibrario
L. Brunet
X. Garros
C. Leroux
M. Casse
Antoine Laurent
A Toffoli
G. Romano
R. Kies
R. Gassilloud
N. Rambal
V. Lapras
M.-P. Samson
C. Tallaron
C. Tabone
B. Previtali
D. Barge
A. Ayres
L. Pasini
P. Besombes
F. Andrieu
P. Batude
T. Skotnicki
M. Vinet
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Citations (2)
Back-end limitations in advanced nodes and alternatives
2017
SISPAD | International Conference on Simulation of Semiconductor Processes and Devices
A. Ayres
Olivier Rozeau
Bertrand Borot
Laurent Fesquet
G. Cibrario
Maud Vinet
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Delay partitioning helps reducing variability in 3DVLSI
2016
ESSDERC | European Solid-State Device Research Conference
A. Ayres
Olivier Rozeau
Bertrand Borot
Laurent Fesquet
Maud Vinet
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Delay partitioning helps reducing variability in 3DVLSI
2016
ESSCIRC | European Solid-State Circuits Conference
A. Ayres
Olivier Rozeau
Bertrand Borot
Laurent Fesquet
Maud Vinet
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Citations (1)
Guidelines on 3DVLSI design regarding the intermediate BEOL process influence
2015
S3S | IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
A. Ayres
O. Rozeau
Bertrand Borot
Laurent Fesquet
G. Cibrario
P. Batude
M. Vinet
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Citations (2)
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