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Thierry Devoivre

STMicroelectronics

12

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105

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In-field in-design metrology target integration for advanced CD and overlay process control via Dosemapper and high order overlay correction for 28nm and beyond logic node

2013 Proceedings of SPIE
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Integration and automation of DoseMapper in a logic fab APC system: application for 45/40/28nm node

2012 Proceedings of SPIE
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Improved CD control for 45-40 nm CMOS logic patterning: anticipation for 32-28 nm

2010 Proceedings of SPIE
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Managing annealing pattern effects in 45nm low power CMOS technology

2009 ESSDERC | European Solid-State Device Research Conference
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Implementation of silicon-validated variability analysis and optimization for standard cell libraries

2008 Proceedings of SPIE
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MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances

2005 ICMTS | International Conference on Microelectronic Test Structures
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65nm OPC and design optimization by using simple electrical transistor simulation

2005
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Element of nonvolatile memory

2005
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Low cost 65nm CMOS platform for Low Power & General Purpose applications

2004 VLSIT | Symposium on VLSI Technology
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Validated 90nm CMOS technology platform with low-k copper interconnects for advanced system-on-chip (SoC)

2002 MTDT | Memory Technology, Design and Testing
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Citations (15)