Back-end limitations in advanced nodes and alternatives

The back-end scaling is increasing the interconnections parasitic elements. In this paper, we analyze the performance of advanced nodes back-end considering a first order evaluation layout. Parasitic elements are extracted and then SPICE simulations were done using compact models for 14, 10, 7 and 5nm. Finally, we present the simulation of possible candidates to increase BEOL performance, such air-gaps and 3D sequential integration.