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Jyh-Rong Lin
Jyh-Rong Lin
Electronic engineering
Materials science
Chip-scale package
Wafer
Composite material
4
Papers
49
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The evaluation of wafer thinning and singulating processes to enhance chip strength
2005
ECTC | Electronic Components and Technology Conference
Shou-Lung Chen
Tzu-Ying Kuo
Hsu-Tien Hu
Jyh-Rong Lin
Shan-Pu Yu
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Citations (27)
Chip-in-substrate package, CiSP, technology
2004
EPTC | Electronics Packaging Technology Conference
Yu-Hua Chen
Jyh-Rong Lin
Shou-Lung Chen
Cheng-Ta Ko
Tzu-Ying Kuo
Chien-Wei Chien
Shan-Pu Yu
A. Ostmann
A Neumann
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The development of enhanced wafer level packaging
2002
EPTC | Electronics Packaging Technology Conference
Wei-Chung Lo
Li Cheng-shen
Shu-Ming Chang
Yu-Chih Chen
Hsu-Tien Hu
Jyh-Rong Lin
Kuo-Chuan Chen
Yu-Jiau Hwang
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The evaluation of flip chip bumping on Cu/low-/spl kappa/ wafer
2002
EPTC | Electronics Packaging Technology Conference
Ruoh-Huey Uang
Shu-Ming Chang
Yu-Chih Chen
Hsu-Tien Hu
Jyh-Rong Lin
Kuo-Chuan Chen
Yu-Jiau Hwang
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Citations (2)
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