The evaluation of flip chip bumping on Cu/low-/spl kappa/ wafer

Recently, flip chip package has obtained more and more attentions due to its benefits of high I/O, low inductance and better thermal dissipation. Therefore flip chip package is getting to be used in some high performance and high speed devices such as microprocessor, chipset, and etc. Today semiconductor fabrication is going to the generation of Cu interconnection and low-/spl kappa/ dielectric in order to meet the Moore's Law. The mechanical (such as hardness, toughness, tensile strength, film stress, CTE and etc.), physical (such as adhesion to metal, thermal stability) and chemical properties of low-/spl kappa/ material, especially the so-called spin-on dielectrics, are very different to those of silicon oxide and nitride because they are composed of soft organic polymer. In flip chip bumping on low-/spl kappa/ dielectric material, the major issue we have to consider is the stress resulted from UBM and solder process will induce the crack or delamination between copper and low-/spl kappa/ dielectric layer. So in this paper we use two kinds of low-/spl kappa/ material, PI 2610 (/spl kappa/=2.9) and SiLK (/spl kappa/=2.6), and two types of UBM material, electroplated copper and electroless nickel, to investigate the influence of UBM material on the mechanical performance of flip chip bumping (e.g. shear force). Besides UBM materials, we would evaluate the effect of UBM size and reflow on bumping quality.