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Satoshi Matsubara

Fujitsu

14

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243

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Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine

2017 CISIS | Complex, Intelligent and Software Intensive Systems
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A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

2010 CSICS | Compound Semiconductor Integrated Circuit Symposium
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A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

2009 CSICS | Compound Semiconductor Integrated Circuit Symposium
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A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS

2009 ISSCC | International Solid-State Circuits Conference
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A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer

2007 ISSCC | International Solid-State Circuits Conference
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Ultra-High-Speed CMOS Interface Technology

2006 Fujitsu Scientific & Technical Journal
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A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization

2005 VLSIC | Symposium on VLSI Circuits
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A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization

2005 IEEE Journal of Solid-state Circuits
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Contrôleur de tension de mode commun

2005
- Kouichi Kanda
- Satoshi Matsubara
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A CMOS multichannel 10-Gb/s transceiver

2003 IEEE Journal of Solid-state Circuits
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Citations (64)