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Syunitirou Masaki
Syunitirou Masaki
Fujitsu
Electronic engineering
Transceiver
Computer science
Communication channel
Clock recovery
4
Papers
59
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A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process
2005
CICC | Custom Integrated Circuits Conference
Yoshiyasu Doi
Syunitirou Masaki
Takaya Chiba
Hirohito Higashi
Hisakatsu Yamaguchi
Hideki Takauchi
Hideki Ishida
Kohtaroh Gotoh
Junji Ogawa
Hirotaka Tamura
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A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization
2005
VLSIC | Symposium on VLSI Circuits
Hirohito Higashi
Syunitirou Masaki
Masaya Kibune
Satoshi Matsubara
Takaya Chiba
Yoshiyasu Doi
Hisakatsu Yamaguchi
Hideki Takauchi
Hideki Ishida
Kohtaroh Gotoh
Hirotaka Tamura
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A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization
2005
IEEE Journal of Solid-state Circuits
Hirohito Higashi
Syunitirou Masaki
Masaya Kibune
Satoshi Matsubara
Takaya Chiba
Yoshiyasu Doi
Hisakatsu Yamaguchi
Hideki Takauchi
Hideki Ishida
Kohtaroh Gotoh
Hirotaka Tamura
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Citations (42)
5-6.4 Gbps 12 channel transceiver with pre-emphasis and equalizer
2004
VLSIC | Symposium on VLSI Circuits
Hirohito Higashi
Syunitirou Masaki
Masaya Kibune
Satoshi Matsubara
Takaya Chiba
Yoshiyasu Doi
Hisakatsu Yamaguchi
Hideki Takauchi
Hideki Ishida
Kohtaroh Gotoh
Hirotaka Tamura
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Citations (13)
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