A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

A 2 x 21.5-22.3 Gb/s to 4 x 10.7-11.2 Gb/s SFI5.2 compliant two-chip SerDes for a 40 Gb/s optical transponder module has been fabricated in 65 nm 12-metal CMOS. The deserializer receives 2 x 20 Gb/s data from a TIA and outputs SFI 5.2 4 x 10 Gb/s data and 10 Gb/s deskew channel. The serializer receives SFI5.2 inputs and outputs 2 x 20 Gb/s for the optical DQPSK modulator. Although inductor-peaked CML is needed in the deserializer 20 Gb/s input limiting amplifier (LA) and the serializer output stages, power reduction to 3 W for both IC's is effected by deserializing to 16 x 2.5 Gb/s internally and implementing the core logic using standard CMOS circuits. Index Terms—SFI 5.2, DQPSK, LA, CDR, Serializer, Deseri- alizer, Mux, Demux. I. INTRODUCTION