Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine

We propose a hardware architecture for solving combinatorial optimization problems and implemented it on an FPGA. The hardware minimizes the energy of Ising model with 1,024 state variables fully connectable through 16-bit weights, which ease restrictions on mapping problems onto the Ising model. The system uses a hardware bit-sieve engine that performs a Markov-chain Monte-Carlo search with a parallel-evaluation of the energy increment prior to the bit selection, achieving a speedup while guaranteeing convergence. The engine is implemented on an Arria 10 GX FPGA and solves 32-city traveling salesman problems 104 times faster than simulated annealing running on a 3.5-GHz Intel Xeon E5-1620v3 processor.