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Hironobu Yamasaki

Fujitsu

5

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37

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Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine

2017 CISIS | Complex, Intelligent and Software Intensive Systems
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An FPGA-accelerated partial duplicate image retrieval engine for a document search system

2016 WACV | Workshop on Applications of Computer Vision
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Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology

2013 ISQED | International Symposium on Quality Electronic Design
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Energy efficient Echo-Hiding extraction method based on fine grain intermittent power control

2012 SAS | Sensors Applications Symposium
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