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C. Prasad

Intel

26

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1323

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Silicon Reliability Characterization of Intel’s Foveros 3D Integration Technology for Logic-on-Logic Die Stacking

2020 IRPS | International Reliability Physics Symposium
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Technology scaling implications for BTI reliability

2018 Microelectronics Reliability
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Self-heating in advanced CMOS technologies

2017 IRPS | International Reliability Physics Symposium
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Aging model challenges in deeply scaled tri-gate technologies

2015 IIRW | International Integrated Reliability Workshop
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A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products

2015 VLSIC | Symposium on VLSI Circuits
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Transistor reliability variation correlation to threshold voltage

2015 IRPS | International Reliability Physics Symposium
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Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures

2014 IRPS | International Reliability Physics Symposium
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Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

2012 IRPS | International Reliability Physics Symposium
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Frequency and recovery effects in high-κ BTI degradation

2009 IRPS | International Reliability Physics Symposium
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Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

2009 IRPS | International Reliability Physics Symposium
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Citations (12)