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Curtis Tsai

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17

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A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products

2015 VLSIC | Symposium on VLSI Circuits
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Transistor architecture with extended recessed spacer and source / drain regions and process for their preparation

2013
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Dispositifs tridimensionnels à haute tension ayant des séparateurs diélectriques

2013
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Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

2013 IRPS | International Reliability Physics Symposium
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A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

2012 IEDM | International Electron Devices Meeting
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Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2 nd generation high-k/metal gate transistors

2011 IRPS | International Reliability Physics Symposium
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A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

2010 VLSIT | Symposium on VLSI Technology
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RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

2010 IEDM | International Electron Devices Meeting
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A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

2009 IEDM | International Electron Devices Meeting
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A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

2008 IEDM | International Electron Devices Meeting
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Citations (36)