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Stephan Brus

Katholieke Universiteit Leuven

6

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Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-DIT Si-cap-free Gate Stack and Optimizing the Channel Strain

2020 VLSIT | Symposium on VLSI Technology
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改良ゲートスタック表面調製によるSi不動態化Ge nFinFETにおける記録GM_SAT/SS_SATとPBTI信頼性【JST・京大機械翻訳】

2019
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Ge oxide scavenging and gate stack nitridation for strained Si 0.7 Ge 0.3 pFinFETs enabling 35% higher mobility than Si

2019 IEDM | International Electron Devices Meeting
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