Low Temperature Atomic Hydrogen Treatment for Superior NBTI Reliability—Demonstration and Modeling across SiO 2 IL Thicknesses from 1.8 to 0.6 nm for I/O and Core Logic

NBTI remains a primary reliability concern for CMOS technology. Contrary to PBTI, which has been continuously reduced in the last five HKMG technology nodes, NBTI has remained virtually unchanged [1] , and is often considered an ineradicable issue. In RMG integration flows, a high-temperature (T~900°C) post-metal anneal is customary to suppress dielectric defectivity. This high thermal budget step is incompatible with novel stacked integration schemes, such as Sequential 3D and CFETs [2] . Furthermore, the so-called ‘reliability anneal’ typically requires a thick sacrificial TiN/a-Si gate, which may become unsuitable for nanosheets with tight vertical spacing. In [3] hydrogen radicals (H*) generated in a low-T remote plasma were used to passivate hole traps associated with the hydroxyl- E ’ (Η- E ’) SiO 2 defects in 1.2nm thick interface layers (IL). These defects form at stretched Si-O bonds and are abundant in IL’s grown at reduced T due to unrelaxed interface strain, causing poor NBTI reliability [3] . In this work, we i) explore the H* treatment process window , ii) optimize the treatment for ultra-thin 0.6nm chemical oxide IL’s (chemOx), focusing on EOT control, and iii) show the applicability for 1.8nm thick IL’s, of relevance for I/O devices.