(Invited) Si-Cap-Free Low-DIT SiGe Gate Stack for High-Performance pFETs

We have demonstrated a metal high-k gate stack with DIT as low as 5.4×1011 cm-2eV-1 at an EOT of 10.9 A on a planar Si0.7Ge0.3 MOS capacitor test vehicle without using a Si-cap. The key enablers of the DIT reduction are GeO scavenging process converting GeO into SiO and gate stack nitridation processes. Although the final DIT was found to be highly sensitive to the metal gate deposition process, nitridation of HfO2 was found to negate the negative impact from ALD-based TiN/W. Additional MOS capacitor experiments suggested that the role of the nitridation of HfO2 is to reduce the oxygen diffusivity, resulting in suppressing the undesired oxygen diffusion from the ALD-based metal electrode through the high-k, and resultant interface layer regrowth with additional GeO formation. These results imply that the oxygen profile control throughout the gate stack process is the key to the low-DIT SiGe gate stack.