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D. Temmler
D. Temmler
Qimonda
Dram
Electrical engineering
Capacitor
Trench
Transistor
4
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2
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0
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Self-Alignment Techniques to enable 40nm Trench Capacitor DRAM Technologies with 3-D Array Transistor and Single-Sided Strap
2007
VLSIT | Symposium on VLSI Technology
Hans-Peter Moll
Jessica Hartwich
Arnd Scholz
D. Temmler
Andrew Graham
S. Slesazek
G. Wedler
Lars Heineck
Tobias Mono
U. Zimmermann
K. Schupke
F. Ludwig
Inho Park
T. Tran
W. Muller
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A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond
2007
IEDM | International Electron Devices Meeting
Lars Heineck
Werner Graf
Martin Popp
D. Savignac
Hans-Peter Moll
R. Tews
D. Temmler
Gouri Sankar Kar
J. Schmid
M. Rouhanian
Ines Uhlig
Matthias Goldbach
Erhard Landgraf
Lars Dreeskornfeld
M. Drubba
S. Lukas
D. Weinmann
Wolfgang Roesner
W. Mueller
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Self-Alignment Techniques to enable 40nm Trench Capacitor DRAM Technologies with 3-D Array Transistor and Single-Sided Strap
2007
Symposium on VLSI Technology
H.-P. Moll
Jessica Hartwich
Andreas Scholz
D. Temmler
Andrew Graham
S. Slesazek
G. Wedler
Lars Heineck
Tobias Mono
Uwe T. Zimmermann
Keean Schupke
Frank Ludwig
Inho Park
Thomas T. Tran
Wolfgang Müller
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Self-Alignment Techniques to enable 40nm Trench Capacitor DRAM Technologies with 3-D Array Transistor and Single-Sided Strap
2007
Symposium on VLSI Technology
H.-P. Moll
Jessica Hartwich
Andreas Scholz
D. Temmler
Andrew Graham
S. Slesazek
G. Wedler
Lars Heineck
Tobias Mono
Uwe T. Zimmermann
Keean Schupke
Frank Ludwig
Inho Park
Thomas T. Tran
Wolfgang Müller
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