A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond

We present for the first time the full integration scheme and 512 Mb product data for a trench DRAM technology targeting the 48 nm node. The key technology enablers are a new cell architecture "wordline over bitline" (WOB) realizing a high degree of self-alignment and small parasitic capacitances, together with high performance periphery devices at reduced internal voltage, and the integration of a MIC/HfSiO trench capacitor.