Self-Alignment Techniques to enable 40nm Trench Capacitor DRAM Technologies with 3-D Array Transistor and Single-Sided Strap

We report an enabling technology for 40 nm trench DRAM and beyond. The 3-dimensional array transistor is formed self-aligned (SA) to the deep trench (DT) capacitor; and the single-sided strap contact (SC) connecting the array transistor to the trench capacitor is formed self-aligned within the deep trench. This technology eliminates critical lithography levels and provides robust process windows for DRAM trench cell scaling to below 40 nm.