Implementation of silicon-validated variability analysis and optimization for standard cell libraries

Leveraging silicon validation, a model-based variability analysis has been implemented to detect sensitivity to systematic variations in standard cell libraries using a model-based solution, to reduce performance spread at the cell level and chip level. First, a simulation methodology to predict changes in circuit characteristics due to systematic lithography and etch effects is described and validated in silicon. This methodology relies on these two foundations: 1) A physical shape model predicts contours from drawn layout; 2) An electrical device model, which captures narrow width effects, accurately reproduces drive currents of transistors based on silicon contours. The electrical model, combined with accurate lithographic contour simulation, is used to account for systematic variations due to optical proximity effects and to update an existing circuit netlist to give accurate delay and leakage calculations. After a thorough validation, the contour-based simulation is used at the cell level to analyze and reduce the sensitivity of standard cells to their layout context. Using a random context generation, the contour-based simulation is applied to each cell of the library across multiple contexts and litho process conditions, identifying systematic shape variations due to proximity effects and process variations and determining their impact on cell delay. This methodology is used in the flow of cell library design to identify cells with high sensitivity to proximity effects and consequently, large variation in delay and leakage. The contour-based circuit netlist can also be used to perform accurate contour-based cell characterization and provide more silicon-accurate timing in the chip-design flow. A cell-variability index (CVI) can also be derived from the cell-level analysis to provide valuable information to chip-level design optimization tools to reduce overall variability and performance spread of integrated circuits at 65nm and below.