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H. Nagase
H. Nagase
NEC
CMOS
Electronic engineering
Copper interconnect
Optoelectronics
Logic gate
4
Papers
3
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0
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RF performance upgrading of low-power 40nm-node CMOS devices by extremely low-resistance partially-thickened local (PTL)-interconnects
2009
IEDM | International Electron Devices Meeting
Kenichiro Hijioka
J. Kawahara
M. Narihiro
I. Kume
A. Tanabe
H. Nagase
H. Yamamoto
Naoya Inoue
Tsuneo Takeuchi
T. Onodera
S. Saito
N. Furutake
Yasuhide Hayashi
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RF Performance Boosting for 40nm-node CMOS Device by Low-k/Cu Dual Damascene Contact
2009
J. Kawahara
Kenichiro Hijioka
I. Kume
H. Nagase
A. Tanabe
Makoto Ueki
H. Yamamoto
T Fukai
Koji Arita
K. Motoyama
Ryohei Kitao
K. Fujii
M Ikeda
Yasuhide Hayashi
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A new direct low-k/Cu dual damascene (DD) contact lines for low-loss (LL) CMOS device platforms
2008
VLSIT | Symposium on VLSI Technology
J. Kawahara
Makoto Ueki
M. Tagami
K. Yako
H. Yamamoto
Fuminori Ito
H. Nagase
S. Saito
N. Furutake
T. Onodera
Tsuneo Takeuchi
Hideki Nakamura
K. Arita
K. Motoyama
E. Nakazawa
K. Fujii
M. Sekine
Norio Okada
Yoshihiro Hayashi
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RF performance boosting for 40nm-node CMOS device by low-k/Cu dual damascene contact
2008
IEDM | International Electron Devices Meeting
J. Kawahara
Kenichiro Hijioka
I. Kume
H. Nagase
A. Tanabe
Makoto Ueki
H. Yamamoto
Fuminori Ito
Naoya Inoue
M. Tagami
N. Furutake
T. Onodera
S. Saito
Tsuneo Takeuchi
T Fukai
M. Asada
Koji Arita
K. Motoyama
Atsushi Nakajima
E. Nakazawa
Ryohei Kitao
K. Fujii
M. Sekine
M Ikeda
Yasuhide Hayashi
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