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E. Nakazawa
E. Nakazawa
Renesas Electronics
Electronic engineering
Logic gate
CMOS
Copper interconnect
Parasitic capacitance
4
Papers
8
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Effects of metal-cap coverage on electro-migration (EM) tolerance for scaled-down Cu interconnects
2011
IITC | International Interconnect Technology Conference
M. Ueki
E. Nakazawa
Ryohei Kitao
S. Hiroshima
T. Kurokawa
N. Furutake
Hironori Yamamoto
Naoya Inoue
Yasuaki Tsuchiya
Yoshihiro Hayashi
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Citations (2)
Highly-reliable molecular-pore-stack (MPS)-SiOCH/Cu interconnects with CoWB metal-cap films
2009
IITC | International Interconnect Technology Conference
M. Tagami
N. Furutake
Naoya Inoue
E. Nakazawa
K. Arita
Yoshihiro Hayashi
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A new direct low-k/Cu dual damascene (DD) contact lines for low-loss (LL) CMOS device platforms
2008
VLSIT | Symposium on VLSI Technology
J. Kawahara
Makoto Ueki
M. Tagami
K. Yako
H. Yamamoto
Fuminori Ito
H. Nagase
S. Saito
N. Furutake
T. Onodera
Tsuneo Takeuchi
Hideki Nakamura
K. Arita
K. Motoyama
E. Nakazawa
K. Fujii
M. Sekine
Norio Okada
Yoshihiro Hayashi
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Citations (1)
RF performance boosting for 40nm-node CMOS device by low-k/Cu dual damascene contact
2008
IEDM | International Electron Devices Meeting
J. Kawahara
Kenichiro Hijioka
I. Kume
H. Nagase
A. Tanabe
Makoto Ueki
H. Yamamoto
Fuminori Ito
Naoya Inoue
M. Tagami
N. Furutake
T. Onodera
S. Saito
Tsuneo Takeuchi
T Fukai
M. Asada
Koji Arita
K. Motoyama
Atsushi Nakajima
E. Nakazawa
Ryohei Kitao
K. Fujii
M. Sekine
M Ikeda
Yasuhide Hayashi
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Citations (1)
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