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S. Biesemans

Katholieke Universiteit Leuven

184

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1922

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Calibrated PSCAR stochastic simulation

2019
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Single exposure EUV of 32nm pitch logic structures: patterning performance on BF and DF masks

2018
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Tunable bandwidth for application-specific SAxP process enhancement

2018
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Pattern uniformity control in integrated structures

2017 Proceedings of SPIE
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Optimized design of Si-cap layer in strained-SiGe channel p-MOSFETs based on computational and experimental approaches

2014 Solid-state Electronics
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Interface Trap Density Metrology of State-of-the-Art Undoped Si n-FinFETs

2011 IEEE Electron Device Letters
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High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO2 Gate Dielectric

2011 Japanese Journal of Applied Physics
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Sub-threshold transport and the role of interface traps in undoped Si n-FinFETs scaled up to the full body inversion limit

2011
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3D stacked IC demonstration using a through silicon via first approach

2011
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Simple current and capacitance methods for bulk finFET height extraction and correlation to device variability

2011 ICMTS | International Conference on Microelectronic Test Structures
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