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L. Gaben

STMicroelectronics

14

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Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

2016 IEDM | International Electron Devices Meeting
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HSQ Lithography for Nanowire First Integration: an Interesting Alternative for Gate Last Fabrication of Sub-7nm Stacked Nanowire FETs.

2016 The Japan Society of Applied Physics
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Stacked Nanowires FETs: Mechanical robustness evaluation for sub-7nm nodes

2016 SNW | IEEE Silicon Nanoelectronics Workshop
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(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities

2016
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内部スペーサとSiGeソース/ドレインをもつ置換金属ゲートプロセスにおける垂直積層NanoWires MOSFET【Powered by NICT】

2016
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Microstructure Analysis of Nanosized Advanced Materials through the ACOM-TEM Technique

2016
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Optimization of Trigate-On-Insulator MOSFET aspect ratio with MASTAR

2015 ESSDERC | European Solid-State Device Research Conference
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P-type trigate nano wires: Impact of nano wire thickness and Si 0.7 Ge 0.3 source-drain epitaxy

2015 EUROSOI-ULIS | Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
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Ω-Gate Nanowire Transistors Realized by Sidewall Image Transfer Patterning: 35nm Channel Pitch and Opportunities for Stacked-Nanowires Architectures

2015
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Opportunities and challenges of nanowire-based CMOS technologies

2015 S3S | IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
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Citations (12)