Old Web
English
Sign In
Acemap
>
authorDetail
>
Yu-Chi Su
Yu-Chi Su
ASML Holding
Engineering
Electronic engineering
Voltage
Logic gate
Silicon on insulator
3
Papers
2
Citations
0
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (3)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
Large area EUV via yield analysis for single damascene process: voltage contrast, CD and defect metrology (Conference Presentation)
2019
Victor M. Blanco Carballo
Sara Paolillo
Marleen van der Veen
Stephane Larivière
Gian Lorusso
Etienne de Poortere
Cyrus Tabery
Fu Qiao
shu-yu lai
Marc Kea
Luke wang
Yu-Chi Su
Joe Oh
jim huang
jimmy chen
jonathan huang
Show All
Source
Cite
Save
Citations (0)
Rapid In-line Process Window Characterization Using Voltage Contrast Test Structures for Advanced FinFET Technology Development
2019
ASMC | Advanced Semiconductor Manufacturing Conference
Weihong Gao
Jeonghee Kim
Hsiao-Chi Peng
Chih-Chung Huang
Oliver D. Patterson
Yu-Chi Su
Hsiang Ting Yeh
Sean Starr-baier
Haokun Hu
Show All
Source
Cite
Save
Citations (2)
Shortest path CD measurement using contour extraction
2018
ASMC | Advanced Semiconductor Manufacturing Conference
Oliver D. Patterson
Bart Seefeldt
Wan-Hsiang Liang
Haokun Hu
Joan Chen
Yu-Chi Su
Hsiang Ting Yeh
Pengcheng Zhang
Show All
Source
Cite
Save
Citations (0)
1