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Michael Roberge
Michael Roberge
IBM
Electronic engineering
Computer science
Dram
Capacitor
Architecture
5
Papers
21
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14nm FinFET 1.5Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing
2019
Eric D. Hunt-Schroeder
Darren L. Anand
John A. Fifield
Michael Roberge
Dale E. Pontius
Mark D. Jacunski
Kevin Batson
Matthew Deming
Faraz Khan
Dan Moy
Alberto Cestero
Robert Katz
Zakariae Chbili
Edmund Banghart
L. Jiang
Balaji Jayaraman
Rajesh Reddy Tummuru
Ramesh Raghavan
Amit Mishra
Norman Robson
Toshiaki Kirihata
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Citations (4)
A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns
2010
CICC | Custom Integrated Circuits Conference
Mark D. Jacunski
Darren L. Anand
Robert E. Busch
John A. Fifield
Matthew Lanahan
Paul Lane
Adrian Paparelli
Gary Pomichter
Dale E. Pontius
Michael Roberge
Stephen Sliva
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Citations (8)
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST
2007
CICC | Custom Integrated Circuits Conference
Darren L. Anand
Jim Covino
Jeffrey H. Dreibelbis
John A. Fifield
Kevin W. Gorman
Mark D. Jacunski
Jake Paparelli
Gary Pomichter
Dale E. Pontius
Michael Roberge
Stephen Sliva
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Citations (3)
Advancements in at-speed array BIST: multiple improvements
2007
ITC | International Test Conference
Kevin W. Gorman
Michael Roberge
Adrian Paparelli
Gary Pomichter
Stephen Sliva
William R. Corbin
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Citations (5)
A 110 nm 512 Mb DDR DRAM with vertical transistor trench cell
2002
VLSIC | Symposium on VLSI Circuits
Stefan Sunnyvale Wuensche
Mark D. Jacunski
H. Streif
Andre Sturm
Jack Morrish
Michael Roberge
M. Clark
T. Nostrand
Ernst Stahl
Scott C. Lewis
J. Heath
M. Wood
T. Vogelsang
Endre Philip Thoma
J. Gabric
M. Kleiner
Michael A. Killian
P. Poechmueller
W. Mueller
Gary B. Bronner
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