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S. Muranaka
S. Muranaka
Renesas Electronics
Logic gate
Electronic engineering
Physics
Nitride
Fin
3
Papers
17
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Reliability and scalability of FinFET split-gate MONOS array with tight Vth distribution for 16/14nm-node embedded flash
2017
IEDM | International Electron Devices Meeting
S. Tsuda
T. Saito
H. Nagase
Y. Kawashima
A. Yoshitomi
Shinobu Okanishi
T. Hayashi
T. Maruyama
Masao Inoue
S. Muranaka
S. Kato
T. Hagiwara
H. Saito
Tadashi Yamaguchi
M. Kadoshima
T. Mihara
Hiroshi Yanagita
K. Sonoda
T. Yamashita
Yasuo Yamaguchi
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Citations (5)
16/14nmノードおよびそれ以上における高速・高信頼性埋込みフラッシュのためのFinFET分割ゲートMONOSの初めての実証【Powered by NICT】
2016
S. Tsuda
Y. Kawashima
K. Sonoda
A. Yoshitomi
T. Mihara
S. Narumi
Masao Inoue
S. Muranaka
T. Maruyama
T. Yamashita
Yasuo Yamaguchi
Digh Hisamoto
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First demonstration of FinFET split-gate MONOS for high-speed and highly-reliable embedded flash in 16/14nm-node and beyond
2016
IEDM | International Electron Devices Meeting
S. Tsuda
Y. Kawashima
K. Sonoda
A. Yoshitomi
T. Mihara
S. Narumi
Masao Inoue
S. Muranaka
T. Maruyama
T. Yamashita
Yasuo Yamaguchi
Digh Hisamoto
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Citations (12)
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