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S. Narumi
S. Narumi
Renesas Electronics
Electronic engineering
Computer science
Parallel computing
Integrated circuit design
Memory architecture
3
Papers
125
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16/14nmノードおよびそれ以上における高速・高信頼性埋込みフラッシュのためのFinFET分割ゲートMONOSの初めての実証【Powered by NICT】
2016
S. Tsuda
Y. Kawashima
K. Sonoda
A. Yoshitomi
T. Mihara
S. Narumi
Masao Inoue
S. Muranaka
T. Maruyama
T. Yamashita
Yasuo Yamaguchi
Digh Hisamoto
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First demonstration of FinFET split-gate MONOS for high-speed and highly-reliable embedded flash in 16/14nm-node and beyond
2016
IEDM | International Electron Devices Meeting
S. Tsuda
Y. Kawashima
K. Sonoda
A. Yoshitomi
T. Mihara
S. Narumi
Masao Inoue
S. Muranaka
T. Maruyama
T. Yamashita
Yasuo Yamaguchi
Digh Hisamoto
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Citations (12)
The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories
2006
VLSIC | Symposium on VLSI Circuits
Hideaki Kurata
Kazuo Otsuga
Akira Kotabe
Shinya Kajiyama
Taro Osabe
Yoshitaka Sasago
S. Narumi
Kenji Tokami
Shiro Kamohara
O. Tsuchiya
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Citations (113)
1