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T. Mihara
T. Mihara
Renesas Electronics
Silicon
Optoelectronics
Logic gate
Electronic engineering
Physics
4
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17
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Fabrication and Evaluation of Split-Gate Type Charge-Trapping Nonvolatile Memory with High-k Trapping and Blocking Layers for Embedded Flash
2021
IWJT | International Workshop on Junction Technology
Y. Z. Wang
A. Amo
E. Tsukuda
Kenichiro Sonoda
R. Ogura
S. Kimura
Tomoya Saito
Tadashi Yamaguchi
T. Mihara
Masao Inoue
T. Ogata
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Reliability and scalability of FinFET split-gate MONOS array with tight Vth distribution for 16/14nm-node embedded flash
2017
IEDM | International Electron Devices Meeting
S. Tsuda
T. Saito
H. Nagase
Y. Kawashima
A. Yoshitomi
Shinobu Okanishi
T. Hayashi
T. Maruyama
Masao Inoue
S. Muranaka
S. Kato
T. Hagiwara
H. Saito
Tadashi Yamaguchi
M. Kadoshima
T. Mihara
Hiroshi Yanagita
K. Sonoda
T. Yamashita
Yasuo Yamaguchi
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Citations (5)
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