INTEGRATED CIRCUITS INTERCONNECT METALLIZATION FOR THE SUBMICRON AGE
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The interconnect metallizationbeing used by the semiconductor industry has been aluminumor aluminum silicon. Aluminumsilicon is being replaced by aluminum copper and aluminum copper silicon, due to its superior resistance to electromigration and hillock growth. This paper discusses the implementation of aluminum copper/silicon alloys in semiconductor processing, along with a review of the problems and advantages of the same.Keywords:
Electromigration
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Semiconductor Industry
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Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrate significant differences because of differences in interconnect architectural schemes. The low critical stress for void nucleation at the Cu and interlevel diffusion-barrier interface leads to varying failure characteristics depending on the via position and configuration in a line. Unlike Al technology, a (jL) product-filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. A methodology and tool for circuit-level interconnect-reliability analyses has been developed. Using data from the literature, the layout-specific circuit-level reliability for Al and dual-damascene Cu metallizations have been compared for various circuits and circuit elements. Significantly improved test-level reliability in Cu is required to achieve equivalent circuit-level reliability. Moreover, the required improvement will increase as low-k/low-modulus dielectrics are introduced, and as liner thicknesses are reduced.
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▪ Abstract The increasingly rapid transition of the electronics industry to high-density, high-performance multifunctional microprocessor Si technology has precipitated migration to new materials alternatives that can satisfy stringent requirements. One of the recent innovations has been the substitution of copper for the standard aluminum-copper metal wiring in order to decrease resistance and tailor RC delay losses in the various hierarchies of the wiring network. This has been accomplished and the product shipped only since the fall of 1998, after more than a decade of intensive development. Critical fabrication innovations include the development of an electroplating process for the copper network, dual-damascence chem-mech polishing (CMP), and effective liner material for copper diffusion barrier and adhesion promotion. The present copper technology provides improved current-carrying capability by higher resistance to electromigration, no device contamination by copper migration, and the performance enhancement analytically predicted. This success of the shift to copper will accelerate the industry movement to finer features and more complex interconnect structures with sufficient device density and connectivity to integrate full systems on chips. The next innovation will be the introduction of low-dielectric constant material that, in combination with copper, will create added excitement as the industry learns how to utilize this new capability.
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The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D integration is studied. Impact of the TSV section size on EM lifetime and consideration of increasing metal level thickness are reported. Void nucleates and grows right after TSV, in the adjacent metal level. The TSV section size at metal level interface is critical for high EM performance. Thickness increase of metal level is revealed to not directly increase EM robustness, since irregular void nucleation and growth impact expected performances.
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A copper-based multilevel metallurgy potentially offers very significant benefits compared to the aluminum alloys and barrier layers that currently are being used in ultralarge-scale integrated (ULSI) technology. However, before copper can be successfully integrated into ULSI systems, a number of important reliability and processing issues must be addressed. At MCNC, a comprehensive program is underway to develop an integrated copper metallurgy process. In this paper, an analysis of the effects of scaling on interconnect delay is given, demonstrating the potential benefits of a copper metallurgy for ULSI circuits. Then, work toward the development of an integrated copper metallurgy process is presented, including copper etching results, a copper cladding methodology to alleviate reliability problems, and a novel via chain structure.
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This paper presents a report of the state of the art with respect to the electromigration phenomenon in integrated circuit (IC) metallization. Reported here are some of the latest research efforts, including the authors' research, on the effects of dielectric overcoatings on electromigration in aluminum interconnections. This research has shown that dielectric overcoating of the aluminum stripes yields interconnections with greater mean time between failures than found in many conventional integrated circuits.
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