Multilevel Metal Using Submicron Copper Interconnects
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Abstract:
A copper-based multilevel metallurgy potentially offers very significant benefits compared to the aluminum alloys and barrier layers that currently are being used in ultralarge-scale integrated (ULSI) technology. However, before copper can be successfully integrated into ULSI systems, a number of important reliability and processing issues must be addressed. At MCNC, a comprehensive program is underway to develop an integrated copper metallurgy process. In this paper, an analysis of the effects of scaling on interconnect delay is given, demonstrating the potential benefits of a copper metallurgy for ULSI circuits. Then, work toward the development of an integrated copper metallurgy process is presented, including copper etching results, a copper cladding methodology to alleviate reliability problems, and a novel via chain structure.Keywords:
Copper interconnect
Copper interconnect
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Dry etching
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A novel Al chemical vapor deposition (CVD) technique called “CVD Al reflow trench fill” was developed using methylpyrrolidine alane (MPA) as a precursor in a damascene structure. The new method is based on the changes in deposition properties of CVD Al with the MPA precursor depending on its under layer. Using this characteristic, we completely filled a 40 nm-spacing trench and confirmed robust electrical properties. These results were again verified by comparing the bit line property of the Al damascene scheme with those of the Al reactive ion etch (RIE) scheme and low resistivity W (LRW) damascene structures.
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The integration of dual damascene-copper/low-k structures requires the development of new cleaning processes and chemistries compatible with the new materials. This study examines the opportunities for plasma cleaning and wet cleaning.
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For future high performance logic semiconductor products it is essential to lower the dielectric constant k of the intra- and interlayer isolators in combination with Cu single and dual damascene metallisation. In this paper we report on the first successful single and dual damascene integration of a porous methylsilsesquioxane based spin-on dielectric, JSR LKD. Deposition, etch, resist strip, clean and CMP behaviour and electrical results from both single and dual damascene integration are discussed.
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Dual damascene patterning is essential for the integration of copper into a high performance interconnect, hence the etching process becomes the most important challenge. This paper described the work on the dual damascene etching. The three most common schemes for patterning the dual damascene structure are trench-first, via-first (also known as counter-bore) and self-aligned etchings. Although only self- aligned etching requires the insertion of a stop layer, the stop layer is crucial to all schemes for a better control of the etching uniformity. The impact of using a stop layer with every dual damascene scheme was investigated. Lithography plays an important role in damascene etching. The use of negative-tone photoresist for metal trench masking and the challenge of forming a residue-free damascene structure in the presence of a bottom anti- reflecting coating were discussed.
Copper interconnect
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In this study, we demonstrate the scaling potential of our damascene redistribution layer (RDL) approach by manufacturing an RDL process using a photosensitive polymer and copper metal lines with a target pitch of 1 μm. Among the various advantages of using a photosensitive dielectric and a damascene approach, the presence of a chemical-mechanical polishing (CMP) step after the copper growth process is key to guarantee the flatness of the stack. Ultimately, it allows for more RDL layer to be patterned at resolution limits. This approach is demonstrated by processing a 4 metal layers RDL with a minimal pitch of 3.2 μm. Collected electrical data as well as FIB cross-sections and SEM imaging performed after various process steps confirm the excellent patterning of the metal wires thus demonstrating the superiority of the damascene approach compared to the semi-additive process.
Copper interconnect
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