Electromigration behavior of 3D-IC TSV interconnects
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Abstract:
The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D integration is studied. Impact of the TSV section size on EM lifetime and consideration of increasing metal level thickness are reported. Void nucleates and grows right after TSV, in the adjacent metal level. The TSV section size at metal level interface is critical for high EM performance. Thickness increase of metal level is revealed to not directly increase EM robustness, since irregular void nucleation and growth impact expected performances.Keywords:
Electromigration
Void (composites)
Through-Silicon Via
Robustness
Three-dimensional integrated circuit
A combined driving force model consisting of three driving forces is implemented for copper dual damascene line-via interconnects using finite element method. Good agreement is found between the experimental and computational results on the void volume at failure and time varying resistance change during electromigration stressing. The void evolution is also computed showing the process of the void growth that lead to the void observed at failure, and it is found that the void grows at the inner corner between the metallization and the via initially. The model predicts that, the driving force from the stress gradient dominates at the very beginning of the mass transport while in the latter stage, the electron-wind force dominates.
Electromigration
Void (composites)
Copper interconnect
The Void
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Kelvin bump probes were fabricated in flip‐chip solder joints, and they were employed to monitor the void formation during electromigration. We found that voids started to form at approximately 5% of the failure time under 0.8 A at 15 °C, and the bump resistance increased only 0.02 mΩ in the initial stage of void formation. Three‐dimensional simulation was performed to examine the increase in bump resistance at different stages of void formation, and it fitted the experimental results quite well. This technique provides a systematic way for investigating the void formation during electromigration.
Electromigration
Void (composites)
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Through-Silicon Via
Three-dimensional integrated circuit
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Three-dimensional integrated circuits (3D ICs) can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogeneous integration. The inter-layer connection, which is generally implemented by the Through-Silicon-Via (TSV), is a key technology for 3D ICs. In this paper, we propose a unified simulated annealing technology to tackle the TSV assignment problem, including the signal TSV assignment of 3D nets and 3D buses. The experiment results show the effective of the method.
Through-Silicon Via
Three-dimensional integrated circuit
Integrated circuit design
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Through silicon vias are the components in three-dimensional integrated circuits, which are responsible for the vertical connection inside the dies. In this work we present studies about the reliability of open through silicon vias against electromigration. A two-step approach is followed. In the first step the stress development of a void free structure is analyzed by means of simulation to find the locations, where voids due to stress are most probably nucleated. In the second step, voids are placed in the through silicon vias and their evolution is traced including the increase of resistance. The resistance raises more than linearly in time and shows an abrupt open circuit failure. Simulations were carried out for different currents and fitted to Black's equation. These results are in good agreement with results of time accelerated electromigration tests.
Electromigration
Void (composites)
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In this study, we examine the effects of void morphology and critical current density (jc) on the electromigration failure distributions of Cu/low-k dual damascene vias. Cu dual damascene vias exhibit multiple modes of electromigration-induced voiding and reliability is strongly dependent on the morphology of voids. We have developed a model of failure for DC and pulsed DC currents that allow prediction of failure time distributions for vias taking into account void morphology. We obtain good agreement between the model predictions and experimental data for all observed void morphologies.
Electromigration
Void (composites)
Copper interconnect
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3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC integration and 3D Si integration since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip could have two surfaces with circuits) is the focus of this investigation. State-of-the-art, key differences, trends of these three technologies, and a 3D integration roadmap are presented.
Three-dimensional integrated circuit
Through-Silicon Via
Integrated circuit packaging
System Integration
Vertical Integration
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3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC/Si integrations since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the heart of 3D IC/Si integrations and is the focus of this investigation. The origin of 3D integration is presented. Also, the evolution, challenges, and outlook of 3D IC/Si integrations are discussed as well as their road maps are presented. Finally, a few generic, low-cost, and thermal-enhanced 3D IC integration system-in-packages (SiPs) with various passive TSV interposers are proposed.
Three-dimensional integrated circuit
Interposer
Through-Silicon Via
Integrated circuit packaging
Vertical Integration
System in package
System Integration
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The pattern dependence of alternating wide and narrow stripe structures was demonstrated in the investigation of electromigration mechanisms. Magnesium accumulated in the portion of the stripe near the cathode and gradually decreased toward the anode. A fatal large void appeared at the current change point near the cathode.
Electromigration
Void (composites)
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Kelvin bump probes were fabricated in flip-chip solder joints, and they were employed to monitor the void formation during electromigration. We found that voids started to form at approximately 5% of the failure time under 0.8A at 150°C, and the bump resistance increased only 0.02mΩ in the initial stage of void formation. Three-dimensional simulation was performed to examine the increase in bump resistance at different stages of void formation, and it fitted the experimental results quite well. This technique provides a systematic way for investigating the void formation during electromigration.
Electromigration
Void (composites)
Cite
Citations (70)