Line-edge roughness (LER) optimization on 300-mm DUV alternating phase shift (altPSM) processes

As critical dimensions (CDs) shrink to 130 nm node and below, LER consumes a substantial amount of CD budget and consequently affects the electrical performance of the circuitry adversely. While phase shift processes and trim etch have been broadly implemented into integration processes, to understand the impact of photo and etch processing parameters on LER and furthermore to control LER becomes crucial. In this paper, the line edge roughness (LER) on DUV 300 mm alternating phase shift processing was characterized as a function of illumination conditions and resist processing parameters. The imaging imbalancing was discussed and demonstrated with rigorous mask topography simulation and the effect of phase shifter on the LER was reported. The CD and LER common process window of iso, dense, and semi-isolated line/space as well as the effect of diluted developer concentration on LER were investigated in order to obtain the robust processes with the lowest LER at reasonable throughput. A molecular dynamic simulator of LER generated by using the concept of Monte Carlo simulation was demonstrated and will be used for further simulation down to 65 nm nodes. Finally, the etch transfer of LER in a BEOL short loop film stack of JSR LKD5109 porous low-k and silicon oxy-carbide was reported and the root cause of LER during etch was investigated by partitioning the etch steps.