Device performance improvement with implantation balancing energy contamination and productivity

Ion implantation technology is widely used in semiconductor manufacturing process. Most of install base for high current implanters use deceleration technology to overcome space charge effect especially important for low energy implants. It is necessary to consider the Energy contamination (EC) effects on devices with thinner gate height. This paper use SRIM simulation and dopant profiles, offline sheet resistance to illustrate the selection of deceleration by considering EC tails beyond the gate height. The device effects using p-type Poly (PPoly) and Source Drain (PSD) implant steps are evaluated in state of art 28nm device flow. The device performance can gain 6% with optimized implant conditions. It demonstrated the necessary of balance device requirement and productivity using implanters with deceleration technologies. The newer generation implanters with EC filter technology, providing maximum productivity while meeting device requirement, was discussed briefly also.