Plasma charging effects on device degradation from via sputter etch

Inductively Coupled Plasma (ICP) and diode sputter etch processes for via filling technology were evaluated in view of the plasma and/or high field damage to the 7 nm gate oxide in both n- and p-channel MOSFETs using 0.35 micrometers CMOS technology. A number of sputter process conditions were considered including the substrate bias, gas flow, and sputter power to examine the threshold voltage instability, drive currents degradation and charge trapping in the gate oxide and the generation of Si/SiO 2 interface traps. Via sizes ranging from 0.5 to 1.0 micrometers were studied for lower and tighter distributions of via resistance. A comparison between ICP and diode sputter processes showed better process robustness for ICP sputter etch than of the diode sputter process. Un- annealed and as processed devices showed as high as 20% change in threshold voltage (V t ) shift and 10% decrease in drive currents for the diode sputter process while the ICP process resulted in as low as 5% change in threshold voltage shift and less than 3% degradation in drive currents. Differences between n- and p-MOSFETs degradation were also observed. The possible process-induced device damage mechanisms will be discussed.