Chip-Package Interaction Challenges for Large Die Applications

To enable higher computing power in a single chip, there is demand for increasing die size for high performance applications in advanced nodes. Due to the weak mechanical properties of the low-k and ultra low-k (ULK) dielectrics in advanced technology nodes, the backend of line (BEOL) stacks are more prone to thermal mechanical failures, resulting in increased semiconductor assembly processes and reliability challenges. This is further exacerbated by the transition of lead (Pb) based solders to Pb-free solders (higher melting temperatures), as well as the transition to copper pillar bump (less malleable / deformable). These changes bring more package stress which can potentially be transferred to the BEOL stack, increasing chip-package interaction (CPI) failure risks. With the increased distance to neutral point (DNP) in large dies, the package to die stress also increases significantly. Therefore, CPI risks in large die applications in advanced nodes are especially challenging. This paper discusses in detail the different CPI reliability challenges of large dies with size up to 25mm x 25mm in flip-chip ball grid array (fcBGA) packages in an advanced CMOS technology node. One of the key findings from this study is the impact of kerf width (crack stop to crack stop distance) on CPI performance. While it is well known that narrow kerfs are more subject to dicing damage risks, it is less recognized that wide kerf poses unique CPI challenges. Both narrow and wide kerf were assessed in this work. It is observed that narrow and wide kerf can drive different failure mechanisms. A wide kerf is especially challenging for CPI due to increased energy release rate of cracks if present. By understanding the physics and mechanics of failures, key CPI sensitive parameters can be defined to ensure products are robust to successfully meet various industry standard CPI stress qualification.