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Frank A. J. M. Driessen

ASML Holding

13

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42

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EUV source-mask optimization for 7nm node and beyond

2014 Proceedings of SPIE
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Advanced OPC Mask-3D and Resist-3D modeling

2014 Proceedings of SPIE
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Advanced OPC Mask-3D and Resist-3D modelling

2014
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Holistic lithography for EUV: NXE:3100 characterization of first printed wafers using an advanced scanner model and scatterometry

2011
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Mask aspects of EUVL imaging at 27nm node and below

2011
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Enhanced layout optimization of sub-45nm standard: memory cells and its effects

2009 Proceedings of SPIE
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DFM software for photomask production and qualification of its accuracy and functionality

2008 Proceedings of SPIE
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Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells

2007
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Full phase-shifting methodology for 65-nm node lithography

2003
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Use of silicon-versus-layout verification (SiVL) in process control of wafer lithography and mask-making metrology

2003
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