Enhanced layout optimization of sub-45nm standard: memory cells and its effects

Automatic layout optimization is becoming an important component of the DfM work flow, as the number of recommended rules and the increasing complexity of trade-offs between them makes manual optimization increasingly difficult and time-consuming. Automation is rapidly becoming the best consistent way to get quantifiable DfM improvements, with their inherent yield and performance benefits for standard cells and memory blocks. Takumi autofixer optimization of Common Platform layouts resulted in improved parametric tolerance and improved DfM metrics, while the cell architecture (size and routability) and the electrical characteristics (speed/power) of the layouts remained intact. Optimization was performed on both GDS-style layouts for standard cells, and on CDBA (Cadence Data Base Architecture)-style layout for memory blocks. This paper will show how trade-offs between various DfM requirements (CAA, recommended rules, and litho) were implemented, and how optimization for memories generated by a compiler was accomplished. Results from this optimization work were verified on 45nm design by model and rule based DfM checking and by wafer yields.