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Michiaki Nakayama

Hitachi

6

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A Method for Measuring of RTN by Boosting Word-Line Voltage in 6-Tr-SRAMs

2014 IEICE Transactions on Electronics
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On-chip dual-ring-oscillator-based random-fluctuation-measurement method for detecting lowest voltage in adaptive voltage scaling systems

2012 A-SSCC | Asian Solid-State Circuits Conference
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A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST

2003 ISSCC | International Solid-State Circuits Conference
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A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation

2000 Technical report of IEICE. ICD
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A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation

2000 ISSCC | International Solid-State Circuits Conference
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