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Mitsugu Kusunoki

Hitachi

5

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34

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A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST

2003 ISSCC | International Solid-State Circuits Conference
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WP 25.3 A 450MHz 64b RISC Processor using Multiple Threshold Voltage CMOS

2000 International Solid-State Circuits Conference
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A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation

2000 Technical report of IEICE. ICD
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