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A. Koshio
A. Koshio
Copper interconnect
Electronic engineering
Dram
high density
Materials science
2
Papers
7
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High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization
2000
Symposium on VLSI Technology
N. Takenaka
M. Segawa
Takashi Uehara
S Akamatsu
Michikazu Matsumoto
K. Kurimoto
T. Ueda
H. Watanabe
T. Matsutani
K. Yoneda
A. Koshio
Yoshiaki Kato
Masahide Inuishi
Toshiyuki Oashi
K. Tsukamoto
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High density embedded DRAM technology with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization
2000
VLSIT | Symposium on VLSI Technology
N. Takenaka
M. Segawa
Takashi Uehara
S Akamatsu
Michikazu Matsumoto
K. Kurimoto
T. Ueda
H. Watanabe
T. Matsutani
K. Yoneda
A. Koshio
Yoshiaki Kato
Masahide Inuishi
Toshiyuki Oashi
K. Tsukamoto
Shigeki Komori
K. Tomita
T. Inbe
R. Ohsaki
T. Hanawa
S. Sakamori
Masayoshi Shirahata
J. Tsuchimoto
T. Eimori
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Citations (7)
1