High density embedded DRAM technology with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization

A high density Embedded DRAM technology has been developed with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC/SRAM. This technology includes (1)W/WNx polymetal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-plugged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology realizes both very small. DRAM cell size of 0.29 /spl mu/m SRAM cell size of 2.77 /spl mu/m/sup 2/ on the same die.