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M. Hirao
M. Hirao
Hitachi
Electronic engineering
Computer science
CMOS
Emitter-coupled logic
Electrical engineering
6
Papers
82
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A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array
1989
ISSCC | International Solid-State Circuits Conference
Masanori Odaka
K. Nakamura
K. Eno
Katsumi Ogiue
O. Saito
T. Ikeda
M. Hirao
Hisayuki Higuchi
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Citations (18)
An 8 ns 256 K BiCMOS RAM
1989
IEEE Journal of Solid-state Circuits
N. Tamba
Shuuichi Miyaoka
Masanori Odaka
Katsumi Ogiue
K. Yamada
T. Ikeda
M. Hirao
Hisayuki Higuchi
Hideaki Uchida
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Citations (16)
A 7-ns/350-mW 64-kbit ECL-compatible RAM
1987
IEEE Journal of Solid-state Circuits
Shuuichi Miyaoka
Masanori Odaka
Katsumi Ogiue
T. Ikeda
Makoto Suzuki
Hisayuki Higuchi
M. Hirao
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Citations (12)
A 7ns/350mW 64K ECL compatible RAM
1987
ISSCC | International Solid-State Circuits Conference
Shuuichi Miyaoka
Masanori Odaka
Katsumi Ogiue
T. Ikeda
Makoto Suzuki
Hisayuki Higuchi
M. Hirao
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A new multilevel interconnection system for submicrometer VLSI's using multilayered dielectrics of plasma Silicon Oxide and low-thermal-expansion polyimide
1987
IEEE Transactions on Electron Devices
Yutaka Misawa
Noriyuki Kinjo
M. Hirao
Shunichi Numata
Naohiro Momma
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Citations (17)
A New Multilevel Interconnection System for Submicron VLSI Using Multilayered Dielectrics of Plasma Silicon Oxide and Low Thermal Expansion Polyimide
1986
VLSIT | Symposium on VLSI Technology
Yutaka Misawa
Noriyuki Kinjo
M. Hirao
Shunichi Numata
Naohiro Momma
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