A 7-ns/350-mW 64-kbit ECL-compatible RAM
1987
A 7-ns 350-mW, 64-kbit ECL RAM was developed using 1.3-/spl mu/m high-performance bipolar-CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 7-GHz cutoff frequency is fabricated together with 1.3-/spl mu/m CMOS. A variable-impedance data-line load, a common data-line equalizing circuit, and a sense-amplifier selection technique together achieve a 7-ns access time. Gates combining bipolar and CMOS devices achieve a power dissipation of one-third that of conventional bipolar 64-kb ECL RAMs.
Keywords:
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
6
References
12
Citations
NaN
KQI