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Takanori Nakao
Takanori Nakao
Fujitsu
Computer science
Electronic engineering
CMOS
Equalizer
Wireline
3
Papers
14
Citations
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A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution
2014
VLSIC | Symposium on VLSI Circuits
Takushi Hashida
Yasumoto Tomita
Yuuki Ogata
Kosuke Suzuki
Shigeto Suzuki
Takanori Nakao
Yuji Terao
Satofumi Honda
Sota Sakabayashi
Ryuichi Nishiyama
Akihiko Konmoto
Yoshitomo Ozeki
Hiroyuki Adachi
Hisakatsu Yamaguchi
Yoichi Koyanagi
Hirotaka Tamura
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Erasure code with shingled local parity groups for efficient recovery from multiple disk failures
2014
HotDep | Hot Topics in System Dependability
Takeshi Miyamae
Takanori Nakao
Kensuke Shiozawa
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An equalizer-adaptation logic for a 25-Gb/s wireline receiver in 28-nm CMOS
2013
A-SSCC | Asian Solid-State Circuits Conference
Takanori Nakao
Yasuo Hidaka
Sota Sakabayashi
Takushi Hashida
Yasumoto Tomita
Yoichi Koyanagi
Hirotaka Tamura
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