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Yuji Terao
Yuji Terao
Fujitsu
Electronic engineering
Computer science
CMOS
CPU multiplier
Parallel computing
3
Papers
6
Citations
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A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution
2014
VLSIC | Symposium on VLSI Circuits
Takushi Hashida
Yasumoto Tomita
Yuuki Ogata
Kosuke Suzuki
Shigeto Suzuki
Takanori Nakao
Yuji Terao
Satofumi Honda
Sota Sakabayashi
Ryuichi Nishiyama
Akihiko Konmoto
Yoshitomo Ozeki
Hiroyuki Adachi
Hisakatsu Yamaguchi
Yoichi Koyanagi
Hirotaka Tamura
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32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE
2013
ISSCC | International Solid-State Circuits Conference
Yuuki Ogata
Yasuo Hidaka
Yoichi Koyanagi
Sadanori Akiya
Yuji Terao
Kosuke Suzuki
Keisuke Kashiwa
Masanobu Suzuki
Hirotaka Tamura
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A Report of 2004 World Econo Move in Akita
2005
Masanori Takahashi
Yuji Terao
Shigeo Tsuchida
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