Old Web
English
Sign In
Acemap
>
authorDetail
>
Sota Sakabayashi
Sota Sakabayashi
Fujitsu
Electronic engineering
Computer science
CMOS
Equalizer
Wireline
3
Papers
21
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (3)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution
2014
VLSIC | Symposium on VLSI Circuits
Takushi Hashida
Yasumoto Tomita
Yuuki Ogata
Kosuke Suzuki
Shigeto Suzuki
Takanori Nakao
Yuji Terao
Satofumi Honda
Sota Sakabayashi
Ryuichi Nishiyama
Akihiko Konmoto
Yoshitomo Ozeki
Hiroyuki Adachi
Hisakatsu Yamaguchi
Yoichi Koyanagi
Hirotaka Tamura
Show All
Source
Cite
Save
Citations (2)
The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server
2013
ISSCC | International Solid-State Circuits Conference
Ryuji Kan
Tomohiro Tanaka
Go Sugizaki
Kinya Ishizaka
Ryuichi Nishiyama
Sota Sakabayashi
Yoichi Koyanagi
Ryuji Iwatsuki
Kazumi Hayasaka
Taiki Uemura
Gaku Ito
Yoshitomo Ozeki
Hiroyuki Adachi
Kazuhiro Furuya
Tsuyoshi Motokurumada
Show All
Source
Cite
Save
Citations (18)
An equalizer-adaptation logic for a 25-Gb/s wireline receiver in 28-nm CMOS
2013
A-SSCC | Asian Solid-State Circuits Conference
Takanori Nakao
Yasuo Hidaka
Sota Sakabayashi
Takushi Hashida
Yasumoto Tomita
Yoichi Koyanagi
Hirotaka Tamura
Show All
Source
Cite
Save
Citations (1)
1